A processor, a system on a chip (SoC), and an application specific integrated circuit (ASIC) can include multiple cores for performing compute operations such as processing digital signals, performing cryptography, executing software applications, rendering graphics, and the like. While there are many multi-core architectures, none of the compilers for these architectures directly address heterogeneous architectures, in particular multi-core processors coupled to reconfigurable/programmable logic (e.g., a field programmable gate array (FPGA) fabric). In addition, existing compilers do not solve the mapping of compute kernels to processor cores and data structures to memory banks, and the routing of stream data and direct memory access (DMA) data between processor cores, and between processor cores and programmable logic.